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IMEC tips streamlined HK+MG steps, touts 32nm high-k, Ta gate improvements
Date: June, 2008
June 17, 2008 - At this week's VLSI Symposium (July 17-20, Hawaii), IMEC says its researchers say they have improved performance in planar CMOS using hafnium-based high-k dielectrics and tantalum-based metal gates for the 32nm node, reduced inverter delay by 33% (15ps to 10ps) and simplified the HK+MG process from 15 steps to nine.
High-performance (low-VT) HK+MG CMOS have been achieved by placing a thin dielectric cap between the gate dielectric and metal gate, with both gate-first and gate-last HK+MG integration schemes proven successful. The gate-last scheme is now being introduced in production for high-performance products, while gate-first is more attractive for low-cost applications -- if it can be simplified to a standard CMOS process flow, IMEC notes in a statement. One of the ways to do this is through a dual-metal dual-dielectric process flow, using mostly hard masks to pattern nMOS and pMOS regions selectively.
IMEC's latest work involves applying conventional stress boosters to its gate-first dual-metal dual-dielectric HK+MG CMOS, which it claims has increased performance of nMOS and pMOS transistors by 16% and 18%, respectively, and improves inverter delay from 15ps to 10ps (see Figures below) -- effectively demonstrating the compatibility of conventional stress memorization techniques with HK+MG.
SEM and x-TEM of nMOS/pMOS boundary in ring oscillator. (Source: IMEC)
Ring oscillator delay comparison of pMOS stress-memorized, dual-metal, dual-dielectric vs. fully FUSI/high-k reference. (Source: IMEC)
Meanwhile, IMEC says it has simplified the process complexity from 15 steps to 9 (a 40% reduction) to a single metal dual-dielectric, by using soft-mask processes and wet removal chemistry, which also allows simpler gate-etch profile control and better scaling prospects. And furthermore, using lanthanum (La) and dysprosium (Dy) capping layers showed no reliability issues, the group said in a statement.
Participants in IMEC's sub-32nm CMOS program include Intel, Micron, Panasonic, Qimonda, Samsung, TSMC, NXP, Elpida, Hynix, Powerchip, Infineon, TI, and STMicroelectronics.
