Immersion lithography-Solid State Technology

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Few steps in the semiconductor manufacturing process are as critical (or expensive) as lithography. Pushing toward leading-edge processes with ultrafine linewidths requires innovations in lithography to expose the chip's layout on the wafer. Entering sub-90nm node manufacturing, this will require new methods including use of water ("immersion lithography"). Researchers and vendors are getting early versions of immersion tools ready for production, in anticipation of full production-level adoption by year's end [WaferNews subscription required to view].

From a technical standpoint, Solid State Technology is at the forefront, exploring immersion lithography's potential to extend 193nm argon-fluoride (ArF) technology to the 45nm process node, and what the 2005 International Technology Roadmap for Semiconductors says about the challenges and requirements for lithography using 193nm immersion. More specifically, Solid State Technology also has examined the process of "stepping and scanning into the NA>1 immersion exposure era".

Even as suppliers continue to tout their progress in immersion, a slew of potential candidates are still being developed and evaluated for the sub-65nm node, including extreme-ultraviolet (EUV) and maskless e-beam lithography. R&D efforts in Europe are ongoing to advance the case for EUV.

As with anything involving heavy development resources, costs are factored into the debate. According to TSMC's Burn Lin, maskless e-beam lithography, specifically e-beam direct, write systems, will be the economic choice at the 22nm node [WaferNews subscription required to view].

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