How Dual Channel Pulse Testing Simplifies Characterizing RF Transistors

Originally Broadcast: March 4, 2008
Overview:
RF and higher power transistors suffer from self-heating and/or trapping effects. These effects, also called dispersion, result in a non-linear response at higher signals. To model the non-linear behavior properly, large signal characterization must be performed. Using pulse IV techniques to characterize the large signal behavior is popular because the interpretation of results leverages ...

 

Atomic Layer Deposition (ALD)

Originally Broadcast: October 31, 2007
Overview:
The webcast will focus on issues surrounding Flash (NAND and NOR) technologies that could be addressed by atomic layer deposition (ALD) as the industry transitions to the 45nm node and below. The discussion will lead into Floating Gate architecture requirements and the associated layers that may require ALD processes, such as IPD (interpoly dielectric) and tunnel oxide layers (SiO2/HfO2). ...

 

Process and Metrology Challenges at 65nm and Beyond: Substrates and Strain

Originally Broadcast: September 28, 2007
Overview:
To complement recent webcasts on metrology for high-k and metal gates, SST will webcast a panel discussion on metrology for advanced silicon substrates using strain engineering technology. Silicon-on-insulator (SOI), solid-phase epitaxy (SPE) in coordination with pre-amorphizing implants (PAI) to achieve alternate channel materials, and strain induced by implantation and thin-film depositions ...

 

Wet Cleans: Dilution/Evolution or Revolution?

Originally Broadcast: September 20, 2007
Overview:
With continued IC dimensional scaling, manufacturing control is now at atomic scales. New cleaning processes must not remove more than one atomic layer of the surface, calling into question the extendibility of the historic RCA wet-clean sequence. The near-term future calls for either an evolution to use ultra-dilute chemistries, or a revolution to use cryo-aerosols, supercritical-CO2 ...

 

Emerging Requirements for Wafer-Level Packaging Metrology

Originally Broadcast: May 23, 2007
Overview:
As the growth in high density, high pin count devices accelerates, so does the need for unique wafer-level packaging (WLP). This webcast will discuss the recent trends in WLP and several of the key process problems and solutions, concentrating on:

• WLP market trends and projections
• WLP design factors that must be met for WLP solutions for devices with high levels of ...